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APW1175
Dual Synchronous DC/DC Controllers with Current Sharing Control
Features
*
Two Operation Modes - Independent Operation - Two-Phase Operation with Current Sharing
General Description
The APW1175 is a two-phase, synchronous, and voltage mode PWM controller to provide dual channel or single outputs in two distinct operation modes. In independent mode, the two PWM converters supply two independently regulated voltages by converting a common or two different power inputs. In two-phase mode, the two PWM converters supply one regulated voltage with programmable current sharing control by converting a common or two different power inputs. The two-phase mode can supply the larger power than that provided each single channel. APW1175 features an internal 300KHz oscillator, VCC Power-On-Reset (POR), an external adjustable soft-start and the programmable output current limit with 50% foldback. The two PWM controllers are 180o out of phase to minimize the input ripple (common power input) and the output ripple (two-phase mode).
*
Driving N-Channel MOSFETs
* 300kHz Constant Frequency Operation * Built-in Feedback Compensation
- Voltage-Mode PWM Control - Fast Transient Response
* 1% VREF Accuracy Over Temperature * Adjustable Output Voltage by an External Resistor Divider * Phase-Shifted Switchers to Minimize Ripple * Current Limit with 50% Fold-Back * Soft-Start and Enable Function * Power-ON Reset (POR) Monitor * Power Good Monitor for Outputs
Pin Description
VR EF +IN 2 -IN 2 VC C C L2C L2+ BST2 DH2 D L2 PGN D
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
Applications
* * * *
Graphics Cards DDR Memory SSTL-2 Termination Power Supply Requiring Two Outputs
GN D PW R GD -IN 1 SS/EN A C L1C L1+ BST1 DH1 D L1 BSTC
Ordering and Marking Information
)29 %#
Lead Free Code Handling Code Tem p. R ange Package Code Package Code K : SO P-20 Tem p. R ange C : 0 to 70C Handling Code TU : Tube TR : Tape & R eel Lead Free Code L : Lead Free D evice Blank : O rginal Device XXXXX - Date Code
APW 1175 K :
APW 1175 XXXXX
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003 1 www.anpec.com.tw
APW1175
Block Diagram
VREF -IN1 CL1CL1+ BSTC
Master Error Amplifier
R Q S
V CL1
BST1 DH1
PWRGD
V REF 1.25V
R Q S
DL1
0.125V
0.125V
OSC
300KHZ
GND
VCC
POWER-ON RESET(POR)
0.125V soft-start control
4V 25uA
BST2
S Q R
DH2 DL2 PGND
SS/ENA
Slave Error Amplifier
V CL2
+IN2
-IN2
CL2-
CL2+
Absolute Maximum Ratings
* * * * * * *
VCC to GND . . . . . . . . . . . . . -0.3V ~ 15V PGND to GND . . . . . . . . . . . . 1V BST to GND . . . . . . . . . . . . . -0.3V ~ 22V Junction Temperature . . . . . . . 150oC Storage Temperature . . . . . . . -65oC ~ 150oC Soldering Temperature . . . 300oC , 10 Seconds Minimum ESD Rating . . . . . . . 3kV
Operating Conditions
* * * *
VCC . . . . . . . . . . . . . . . . . . . . 4.2V ~ 15V BST. . . . . . . . . . . . . . . . . . . . . 5V ~ 17V Ambient Temperature Range . . . 0oC to 85oC Junction Temperature Range. . . . 0oC to 125oC
Thermal Characteristics
Symbol R JA Parameter Thermal Resistance in Free Air SOIC SOIC(with 3in of Copper) Rating 75 65 Unit C/W
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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APW1175
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=4.75~5.25V, GND=PGND=0V, and T)=0~85C. Typical values refer to T)=25C.
S ym b o l P aram eter Test C o n d itio n s AP W 1175 M in Typ 9 2.8 1.6 M ax U n it
S U P P LY C U R R E N T ICC IBSTC IBST1,2 V C C S upply C urrent B S T C S upply C urrent B S T 1,2 S upply C urrent V C C =5~15V , F O S C =300k H z B S T C =5V , D L1,2=O pen, F O S C =300k H z B S T 1,2=10V , D H 1,2=O pen, F O S C =300k H z V C C R ising 270 DH1 DH2 80 mA mA mA
P O W E R -O N R E S E T V C C P O R T hreshold Voltage O S C IL L AT O R F OSC O scillator F requency M axim um D uty C ycle
3.6 300 90 100 1.1 35 0.5
4.2 330
V KHz % V dB
R am p A m plitude V OSC E R R O R AM P L IF IE R A OL E rror A m plifier Voltage G ain Input B ias C urrent Input Voltage = 1.25V (-IN 1, +IN 2, -IN 2) R E F E R E N C E V O LTAG E V REF R eference Voltage V R E F Load R egulation V R E F Line R egulation M easure P in 1 IREF = 1m A V C C = 5~15V 1 0.5 1 0.5 1 0.5 1 0.5 50 60 V O U T =0 V circuit) (refer to ap plica tio n 1.25 1.238
1
A
1.250 3.5
1.262
V mV
0.5
% A A A A
P W M C O N T R O L L E R S G AT E D R IV E R S B S T H -D H =5V D H S ource B S T H -D H =2.5V D H -P G N D =3.5V D H S ink D H -P G N D =1.75V B S T L-D L=5V D L S ource B S T L-D L=2.5V D L-P G N D =3.5V D L S ink D L-P G N D =1.75V D ead Tim e C U R R E N T L IM IT P R O T E C T IO N V CL C urrent Lim it Voltage F old B ack C urrent F old B ack Voltage K nee S O F T -S TAR T ISS S oft-S tart C urrent S oft-S tart Transition
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
200 70 50% V OUT 25 3.3 80
nS mV ILIM V A V
I=ILIM (refer to application circuit) V S S =1V S ynchronous P W M
3
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APW1175
Electrical Characteristics Cont.
Symbol POWER GOOD Upper -IN1 Threshold Lower IN1 Threshold Upper IN2 Threshold Lower IN2 Threshold PWRGD Voltage Low IPWRGD=-5mA 110% 90% V+IN2 +0.1VREF 90% 0.8 VREF VREF V VREF V Parameter Test Conditions APW1175 Min Typ Max Unit
Functional Pin Description
VREF (Pin 1) Internal 1.25V reference voltage . This pin is internally connected to the positive input of the master channel error amplifier. +IN2 (Pin 2) Positive input of the slave channel error amplifier. Connect this pin to 1.25V reference (Pin 1) for the two independent channel configuration. -IN2, -IN1 (Pin 3, 18) Negative inputs of the slave and master error amplifier. VCC (Pin 4) Connect this pin to 5V~15 V power to provides the bias for the control circuitry. Need a 1uF multi-layer ceramic decoupling capacitor to GND (Pin 20). The voltage at this pin is also monitored for Power-On Reset (POR) purpose. CL2-, CL2+, CL1+, CL1- (Pin 5,6,15,16) Current sense input pins. Connect the positive and negative inputs to output current sense resistor for each channel. A current limit comparator for each channel to limit the output current while the difference voltage between the positive and negaive inputs is greater than the 75mV reference. A RC filter is required for noise rejection.
BST2,BST1 (Pin 7,14) Power inputs to the high-side MOSFET drivers. A bootstrap circuit may be used to pump a boot voltage .
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003 4 www.anpec.com.tw
DH2, DH1 (Pin 8,13) High-side MOSFET drivers to provide strong drive current to drive each high-side MOSFET. A small series resistor to the gate of the MOSFET maybe required for each pin. DL2, DL1 (Pin 9,12) Low-side MOSFET drivers to provide strong drive current to drive each low-side MOSFET. A small series resistor to the gate of the MOSFET maybe required for each pin. PGND (Pin 10) Power ground connection. The pin provide the path for return of gate drive currents. BSTC (Pin 11) This pin provide supply voltage to the low-side MOSFET drivers. SS/ENA (Pin 17) Connect a capacitor from this pin to ground.This capacitor, along with an internal 25uA current source, sets the soft-start interval, preventing the outputs from overshoot as well as limiting the input current. Pull this pin to below 1.4V to shutdown the outputs PWRGD (Pin 19) Power good signal output pin. This pin is an open collector output, which is pulled low if the output voltage is outside the power good window. GND (Pin 20) Signal ground for the control circuitry. All voltage levels are measured with respect to this pin.
Q1 AP M 4416
+12V
C1 100uF 16V R1 2 .2 R3 2 .2 1N 4148 D1 Q2 AP M 4416 R4 2 .2 R5 100 L1 7 .5 u H 16V 16V 100uF 100uF 1uF C2 C3 C5
+5V
R2 2 .2 0 .2 2 u F C4
R6 6m
2 .5 V / 6 A
C12 150uF C7 C6 0 .2 2 u F R7 6V 124
PW RO K
C13
C14
150uF
150uF
6V
6V
GND PW RGD - IN 1 S S /E N A C L1C L1+ BST1 DH1 DL1 BSTC
10nF
VREF + IN 2 - IN 2 VCC C L2C L2+ BST2 DH2 DL2 PG ND
C8 10nF
C9 10nF C10 0 .2 2 u F C11 10nF C22 1uF C23 1nF R11 Q3 100 AP M 4416 L2 4 .7 u H C21 R8 124 R9 220
R10
100
1 .8 V / 6 A
R12 6m C15 150uF 6V
C16
C17
150uF
150uF
Typical Application
+5V
C18 C19 150uF 6V 150uF 6V C20 150uF 6V R13 2 .2 D2 1N 4148
6V
6V
1uF
1. Independent Operation
APW1175
Q4 AP M 4416 R14 2 .2 R15 2 .2
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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Q1
+12V
C1 100uF 16 V R1 2.2 1N 4148 R3 2.2 D1 16 V 16 V 100uF 100uF 1uF C2 C3 C5
APM 4416
Q2 APM 4416 R4 2.2 R5 10 0 C6
L1 7 .5 u H
+5V
R2 2.2 0 .2 2 u F C4
R6 6m
2 .7 V / 1 2 A
10nF C7 0 .2 2 u F C9 150uF R7 6V 15 0
PW ROK
C 10
C 11
150uF
150uF
6V
6V
GND PW RGD - IN 1 S S /E N A C L1C L1+ B ST1 DH1 DL1 BSTC
2. Two-Phase Operation with Current Sharing Control
VREF + IN 2 - IN 2 VCC C L2C L2+ B ST2 DH2 DL2 PGND
C8 R 11 22k 10nF R8 12 4
C 15 1uF
C 16 1nF
C 17 10nF R9 Q3 10 0 APM 4416 C 18 L2 4 .7 u H R 10 6m
Typical Application
+5V
C 12 150uF 6V C 13 150uF 6V C 14 150uF 6V R 12 2.2 D2 1N 4148
1uF
APW1175
Q4 APM 4416 R 13 2.2 R 14 2.2
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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APW1175
Packaging Information
SO 300mil ( Reference JEDEC Registration MS-013)
D N
H
E
GAUGE PLANE
123 A e B A1 L 1
Millimeters Dim A A1 B D E e H L N 1 Min. 2.35 0.10 0.33 Max. 2.65 0.30 0.51
Variations- D Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 10.10 11.35 12.60 15.20 17.70 8.80 Max. 10.50 11.76 13 15.60 18.11 9.20 Dim A A1 B D E e H L N 1
Inches Min. 0.093 0.004 0.013 Max. 0.1043 0.0120 0.020
Variations- D Variations SO-16 SO-18 SO-20 SO-24 SO-28 SO-14 Min. 0.398 0.447 0.496 0.599 0.697 0.347 Max. 0.413 0.463 0.512 0.614 0.713 0.362
See variations 7.40 7.60
See variations 0.2914 0.2992
1.27BSC 10 0.40 10.65 1.27
0.050BSC 0.394 0.016 0.419 0.050
See variations 0 8
See variations 0 8
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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APW1175
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
temperature
Peak temperature 183C Pre-heat temperature
Classification Reflow Profiles
Convection or IR/ Convection Average ramp-up rate(183C to Peak) 3C/second max. 120 seconds max Preheat temperature 125 25C) 60 150 seconds Temperature maintained above 183C Time within 5C of actual peak temperature 10 20 seconds Peak temperature range 220 +5/-0C or 235 +5/-0C Ramp-down rate 6 C /second max. 6 minutes max. Time 25C to peak temperature
Time
VPR 10 C /second max. 60 seconds 215-219C or 235 +5/-0C 10 C /second max.
Package Reflow Conditions
pkg. thickness 2.5mm and all bgas Convection 220 +5/-0 C VPR 215-219 C IR/Convection 220 +5/-0 C pkg. thickness < 2.5mm and pkg. volume 350 mm pkg. thickness < 2.5mm and pkg. volume < 350mm Convection 235 +5/-0 C VPR 235 +5/-0 C IR/Convection 235 +5/-0 C
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APW1175
Reliability test program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121C -65C ~ 150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , IJH > 100mA
t Po P P1 D
Carrier Tape
E
F W
Bo
Ao
D1 T2
Ko
J C A B
T1
Application SOP- 20
A 3301 F
B 62 1.5 D
C 12.75 + 0.15 D1
J
T1
T2
2 + 0.6 24.4 + 0.2 2 0.2 Po P1 Ao
W 24 + 0.3 -0.1 Bo 13 0.1
P
E
12 + 0.1 1.75 0.1 t 0.350.01 2.5 0.1 3 Ko
11.5 0.1 1.5 +0.1 1.5+ 0.25 4.0 0.1 2.0 0.1 8.2 0.1
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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APW1175
Cover Tape Dimensions
Application SOP- 20 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 1000
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. A.3 - July., 2003
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